Area efficient on-the-fly error correction code (ECC) decoder architecture

ABSTRACT

Area efficient on-the-fly error correction code (ECC) decoder architecture. A novella means is presented by which only 2 banks of registers are employed (as opposed to 3 or more banks) when generating an error location polynomial in accordance with decoding of a Reed-Solomon (RS) coded signal. Berlekamp-Massey decoding processing can be employed when decoding such a RS coded signal. This approach provides for a significant amount of savings in hardware. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Moreover, because of the pipelined arrangement of the decoding processing presented herein (which allows for more clock cycles to perform the division), division processing can be performed using an inverter and multiplier.

CROSS REFERENCE TO RELATED PATENTS/PATENT APPLICATIONS Provisional Priority Claims

The present U.S. Utility Patent Application claims priority pursuant to 35 U.S.C. § 119(e) to the following U.S. Provisional Patent Applications which are hereby incorporated herein by reference in their entirety and made part of the present U.S. Utility patent application for all purposes:

1. U.S. Provisional Application Ser. No. 60/878,553, entitled “Area efficient on-the-fly error correction code (ECC) decoder architecture,” (Attorney Docket No. BP5586), filed Jan. 4, 2007, pending.

2. U.S. Provisional Application Ser. No. 60/899,522, entitled “Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation,” (Attorney Docket No. BP5587), filed Feb. 5, 2007, pending.

Incorporation by Reference

The following U.S. Utility patent application is hereby incorporated herein by reference in its entirety and is made part of the present U.S. Utility patent application for all purposes:

1. U.S. Utility patent application Ser. No. ______, entitled “Simplified RS (Reed-Solomon) code decoder that obviates error value polynomial calculation,” (Attorney Docket No. BP5587), filed concurrently on Mar. 13, 2007, pending.

BACKGROUND OF THE INVENTION

1. Technical Field of the Invention

The invention relates generally to decoders; and, more particularly, it relates to decoders that are operable to decode Reed-Solomon (RS) coded signals including those that can be implemented within various hard disk drive (HDD) applications.

2. Description of Related Art

Data communication systems have been under continual development for many years. One such type of communication system that has been of significant interest lately is a communication system that employs iterative error correction codes. One type of communication system that has received interest in recent years has been one which employs Reed-Solomon (RS) codes (one type of iterative error correcting code). Communications systems with iterative codes are often able to achieve lower bit error rates (BER) than alternative codes for a given signal to noise ratio (SNR).

A continual and primary directive in this area of development has been to try continually to lower the SNR required to achieve a given BER within a communication system. The ideal goal has been to try to reach Shannon's limit in a communication channel. Shannon's limit may be viewed as being the data rate to be used in a communication channel, having a particular SNR, that achieves error free transmission through the communication channel. In other words, the Shannon limit is the theoretical bound for channel capacity for a given modulation and code rate.

There are a wide variety of applications in which RS codes can be employed to attempt to effectuate (ideally) error free transmission and receipt of information. In the context of communication systems having a communication channel over which coded signals are communicated, RS codes can be employed to attempt to effectuate (ideally) error free transmission from a communication device and/or (ideally) error free receipt of information to a communication device. In the context of hard disk drive (HDD) applications, RS codes can be employed to attempt to effectuate (ideally) error free write and/or read of information to and from storage media. With respect to HDD applications, as is known, many varieties of memory storage devices (e.g. disk drives), such as magnetic disk drives are used to provide data storage for a host device, either directly, or through a network such as a storage area network (SAN) or network attached storage (NAS). Typical host devices include stand alone computer systems such as a desktop or laptop computer, enterprise storage devices such as servers, storage arrays such as a redundant array of independent disks (RAID) arrays, storage routers, storage switches and storage directors, and other consumer devices such as video game systems and digital video recorders. These devices provide high storage capacity in a cost effective manner.

One of the operations performed in decoding a RS coded signal is the generation of an error location polynomial. Generally, prior art approaches require 3 or more banks of registers (or 3 or more memory devices) to store the various coefficients that are calculated and employed to generate this error location polynomial.

BRIEF SUMMARY OF THE INVENTION

The present invention is directed to apparatus and methods of operation that are further described in the following Brief Description of the Several Views of the Drawings, the Detailed Description of the Invention, and the claims. Other features and advantages of the present invention will become apparent from the following detailed description of the invention made with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1 illustrates an embodiment of a disk drive unit.

FIG. 2 illustrates an embodiment of an apparatus that includes a disk controller.

FIG. 3A illustrates an embodiment of a handheld audio unit.

FIG. 3B illustrates an embodiment of a computer.

FIG. 3C illustrates an embodiment of a wireless communication device.

FIG. 3D illustrates an embodiment of a personal digital assistant (PDA).

FIG. 3E illustrates an embodiment of a laptop computer.

FIG. 4 illustrates an embodiment of a communication system.

FIG. 5 illustrates an embodiment of a Reed-Solomon (RS) decoder.

FIG. 6 illustrates an embodiment of error location polynomial generation being performed using only 2 banks of registers in accordance with decoding of a RS coded signal.

FIG. 7 illustrates an embodiment of a variant of Berlekamp-Massey decoding processing that can be employed when decoding a RS coded signal.

FIG. 8 illustrates an embodiment of error location polynomial generation and error location searching being performed using only 2 banks of registers in accordance with decoding of a RS coded signal.

FIG. 9 illustrates an embodiment of a decoding architecture that employs Berlekamp-Massey decoding processing when decoding a RS coded signal.

FIG. 10 illustrates an embodiment of a error location searching and error magnitude (value) calculation in accordance with decoding of a RS coded signal.

FIG. 11 illustrates an embodiment of a method that is operable to employ Berlekamp-Massey decoding processing when decoding a RS coded signal.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 illustrates an embodiment of a disk drive unit 100. In particular, disk drive unit 100 includes a disk 102 that is rotated by a servo motor (not specifically shown) at a velocity such as 3600 revolutions per minute (RPM), 4200 RPM, 4800 RPM, 5,400 RPM, 7,200 RPM, 10,000 RPM, 15,000 RPM; however, other velocities including greater or lesser velocities may likewise be used, depending on the particular application and implementation in a host device. In one possible embodiment, disk 102 can be a magnetic disk that stores information as magnetic field changes on some type of magnetic medium. The medium can be a rigid or non-rigid, removable or non-removable, that consists of or is coated with magnetic material.

Disk drive unit 100 further includes one or more read/write heads 104 that are coupled to arm 106 that is moved by actuator 108 over the surface of the disk 102 either by translation, rotation or both. A disk controller 130 is included for controlling the read and write operations to and from the drive, for controlling the speed of the servo motor and the motion of actuator 108, and for providing an interface to and from the host device.

FIG. 2 illustrates an embodiment of an apparatus 200 that includes a disk controller 130. In particular, disk controller 130 includes a read/write channel 140 for reading and writing data to and from disk 102 through read/write heads 104. Disk formatter 125 is included for controlling the formatting of data and provides clock signals and other timing signals that control the flow of the data written to, and data read from disk 102. Servo formatter 120 provides clock signals and other timing signals based on servo control data read from disk 102. Device controllers 105 control the operation of drive devices 109 such as actuator 108 and the servo motor, etc. Host interface 150 receives read and write commands from host device 50 and transmits data read from disk 102 along with other control information in accordance with a host interface protocol. In one embodiment, the host interface protocol can include, SCSI, SATA, enhanced integrated drive electronics (EIDE), or any number of other host interface protocols, either open or proprietary that can be used for this purpose.

Disk controller 130 further includes a processing module 132 and memory module 134. Processing module 132 can be implemented using one or more microprocessors, micro-controllers, digital signal processors, microcomputers, central processing units, field programmable gate arrays, programmable logic devices, state machines, logic circuits, analog circuits, digital circuits, and/or any devices that manipulates signal (analog and/or digital) based on operational instructions that are stored in memory module 134. When processing module 132 is implemented with two or more devices, each device can perform the same steps, processes or functions in order to provide fault tolerance or redundancy. Alternatively, the function, steps and processes performed by processing module 132 can be split between different devices to provide greater computational speed and/or efficiency.

Memory module 134 may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static random access memory (SRAM), dynamic random access memory (DRAM), flash memory, cache memory, and/or any device that stores digital information. Note that when the processing module 132 implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory module 134 storing the corresponding operational instructions may be embedded within, or external to, the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. Further note that, the memory module 134 stores, and the processing module 132 executes, operational instructions that can correspond to one or more of the steps or a process, method and/or function illustrated herein.

Disk controller 130 includes a plurality of modules, in particular, device controllers 105, processing module 132, memory module 134, read/write channel 140, disk formatter 125, and servo formatter 120 that are interconnected via bus 136 and bus 137. The host interface 150 can be connected to only the bus 137 and communicates with the host device 50. Each of these modules can be implemented in hardware, firmware, software or a combination thereof, in accordance with the broad scope of the present invention. While a particular bus architecture is shown in FIG. 2 with buses 136 and 137, alternative bus architectures that include either a single bus configuration or additional data buses, further connectivity, such as direct connectivity between the various modules, are likewise possible to implement the features and functions included in various embodiments.

In one possible embodiment, one or more modules of disk controller 130 are implemented as part of a system on a chip (SoC) integrated circuit. In an embodiment, this SoC integrated circuit includes a digital portion that can include additional modules such as protocol converters, linear block code encoding and decoding modules, etc., and an analog portion that includes device controllers 105 and optionally additional modules, such as a power supply, etc. In a further embodiment, the various functions and features of disk controller 130 are implemented in a plurality of integrated circuit devices that communicate and combine to perform the functionality of disk controller 130.

When the drive unit 100 is manufactured, disk formatter 125 writes a plurality of servo wedges along with a corresponding plurality of servo address marks at equal radial distance along the disk 102. The servo address marks are used by the timing generator for triggering the “start time” for various events employed when accessing the media of the disk 102 through read/write heads 104.

FIG. 3A illustrates an embodiment of a handheld audio unit 51. In particular, disk drive unit 100 can be implemented in the handheld audio unit 51. In one possible embodiment, the disk drive unit 100 can include a small form factor magnetic hard disk whose disk 102 has a diameter 1.8″ or smaller that is incorporated into or otherwise used by handheld audio unit 51 to provide general storage or storage of audio content such as motion picture expert group (MPEG) audio layer 3 (MP3) files or Windows Media Architecture (WMA) files, video content such as MPEG4 files for playback to a user, and/or any other type of information that may be stored in a digital format.

FIG. 3B illustrates an embodiment of a computer 52. In particular, disk drive unit 100 can be implemented in the computer 52. In one possible embodiment, disk drive unit 100 can include a small form factor magnetic hard disk whose disk 102 has a diameter 1.8″ or smaller, a 2.5″ or 3.5″ drive or larger drive for applications such as enterprise storage applications. Disk drive 100 is incorporated into or otherwise used by computer 52 to provide general purpose storage for any type of information in digital format. Computer 52 can be a desktop computer, or an enterprise storage devices such a server, of a host computer that is attached to a storage array such as a redundant array of independent disks (RAID) array, storage router, edge router, storage switch and/or storage director.

FIG. 3C illustrates an embodiment of a wireless communication device 53. In particular, disk drive unit 100 can be implemented in the wireless communication device 53. In one possible embodiment, disk drive unit 100 can include a small form factor magnetic hard disk whose disk 102 has a diameter 1.8″ or smaller that is incorporated into or otherwise used by wireless communication device 53 to provide general storage or storage of audio content such as motion picture expert group (MPEG) audio layer 3 (MP3) files or Windows Media Architecture (WMA) files, video content such as MPEG4 files, JPEG (joint photographic expert group) files, bitmap files and files stored in other graphics formats that may be captured by an integrated camera or downloaded to the wireless communication device 53, emails, webpage information and other information downloaded from the Internet, address book information, and/or any other type of information that may be stored in a digital format.

In a possible embodiment, wireless communication device 53 is capable of communicating via a wireless telephone network such as a cellular, personal communications service (PCS), general packet radio service (GPRS), global system for mobile communications (GSM), and integrated digital enhanced network (iDEN) or other wireless communications network capable of sending and receiving telephone calls. Further, wireless communication device 53 is capable of communicating via the Internet to access email, download content, access websites, and provide steaming audio and/or video programming. In this fashion, wireless communication device 53 can place and receive telephone calls, text messages such as emails, short message service (SMS) messages, pages and other data messages that can include attachments such as documents, audio files, video files, images and other graphics.

FIG. 3D illustrates an embodiment of a personal digital assistant (PDA) 54. In particular, disk drive unit 100 can be implemented in the personal digital assistant (PDA) 54. In one possible embodiment, disk drive unit 100 can include a small form factor magnetic hard disk whose disk 102 has a diameter 1.8″ or smaller that is incorporated into or otherwise used by personal digital assistant 54 to provide general storage or storage of audio content such as motion picture expert group (MPEG) audio layer 3 (MP3) files or Windows Media Architecture (WMA) files, video content such as MPEG4 files, JPEG (joint photographic expert group) files, bitmap files and files stored in other graphics formats, emails, webpage information and other information downloaded from the Internet, address book information, and/or any other type of information that may be stored in a digital format.

FIG. 3E illustrates an embodiment of a laptop computer 55. In particular, disk drive unit 100 can be implemented in the laptop computer 55. In one possible embodiment, disk drive unit 100 can include a small form factor magnetic hard disk whose disk 102 has a diameter 1.8″ or smaller, or a 2.5″ drive. Disk drive 100 is incorporated into or otherwise used by laptop computer 52 to provide general purpose storage for any type of information in digital format.

FIG. 4 is a diagram illustrating an embodiment of a communication system 400.

Referring to FIG. 4, this embodiment of a communication system 400 is a communication channel 499 that communicatively couples a communication device 410 (including a transmitter 412 having an encoder 414 and including a receiver 416 having a decoder 418) situated at one end of the communication channel 499 to another communication device 420 (including a transmitter 426 having an encoder 428 and including a receiver 422 having a decoder 424) at the other end of the communication channel 499. In some embodiments, either of the communication devices 410 and 420 may only include a transmitter or a receiver. There are several different types of media by which the communication channel 499 may be implemented (e.g., a satellite communication channel 430 using satellite dishes 432 and 434, a wireless communication channel 440 using towers 442 and 444 and/or local antennae 452 and 454, a wired communication channel 450, and/or a fiber-optic communication channel 460 using electrical to optical (E/O) interface 462 and optical to electrical (O/E) interface 464)). In addition, more than one type of media may be implemented and interfaced together thereby forming the communication channel 499.

The signals employed within this embodiment of a communication system 400 can be Reed-Solomon (RS) coded signals. Any of a very wide variety of applications that employ RS coding can benefit from various aspects of the invention, including any of those types of communication systems depicted in FIG. 4. Moreover, other types of devices and applications (e.g., including those employ some type of HDD) that employ RS coding can also benefit from various aspects of the invention.

FIG. 5 illustrates an embodiment of a Reed-Solomon (RS) decoder 500. This is a general depiction of an architecture of a RS decoder 500, and it is noted that variations and/or modifications thereof may be performed without departing from the scope and spirit of the invention. At a minimum, the RS decoder includes an error locator polynomial generation module 520 and an error location search module 530.

A corresponding RS encoder (not shown in this particular embodiment) takes data (e.g., a block of digital data) and adds redundancy or parity bits thereto thereby generating a codeword (e.g., a codeword to be written, transmitted, and/or launched into a communication channel). This redundancy is generated as a function of the particular RS code employed. Therefore, when the data (after undergoing RS encoding) is provided to some storage media (and/or transmitted via a communication channel and/or launched into a communication channel), and after it is read there from (or received there from), in the undesirable event that any errors occurred during either of these processes (write and/or read or transmit and/or receive), hopefully the number of errors incurred is less than the error correcting capability of the RS code. The number and types of errors that can be corrected depends on the particular characteristics of the RS code employed.

Looking at FIG. 5, a received codeword 591 can be viewed as being the originally transmitted (or written) codeword plus any errors that have been incurred during the write and/or read processes to the media or during the transmission and/or receipt of a RS coded signal. In addition, such as in the context of HDD applications, perhaps some defects occurred to the actual physical surface of the storage media after the codeword has been written. This received codeword would then also include those incurred errors as well. Generally speaking, the RS decoder 500 attempts to identify the locations and magnitudes of any errors within the received codeword 591 (up to the error correcting capability of the RS code) and to correct those errors.

A syndrome calculation module 510 then processes the received codeword 591 to generate syndromes 592. The operation of the syndrome calculation module 510 is analogous and similar to the calculation of the redundancy or parity bits within the RS encoding processing. As a function of the RS code employed, a RS codeword has a predetermined number of syndromes that depend only on errors (i.e., not on the actually written or transmitted codeword). The syndromes can be calculated by substituting a predetermined number of roots (as determined by the RS code) of the generator polynomial (employed within RS encoding) into the received codeword 591.

An error locator polynomial generation module 520 then receives these calculated syndromes 592. The syndromes 592 are also passed to an error magnitude calculation module 540. The error locator polynomial generation module 520 can generate the error locator polynomial 593 using various means, two of which can include the Berlekamp-Massey method 522 or Euclid method 524.

The error locator polynomial 593 is provided to an error correction module 550. The error locator polynomial 593 is also provided to an error location search module 530 that is operable to solve for the roots of the error locator polynomial 593. One approach is to employ the Chien search function 532.

Once the error locations 594 have been found within the error location search module 530 (i.e., using the Chien search function 532), then the error locations 594 are provided to the error magnitude calculation module 540 as well as to the error correction module 550. The error magnitude calculation module 540 finds the symbol error values, and it can employ a known approach such as the Forney method 542. Once the error locations 594 and the error magnitudes 595 are known, then the error correction module 550 corrects for them and outputs an estimated codeword 596.

With respect to the various processing modules depicted in this diagram as well as others, it is noted that any such processing module may be a single processing device or a plurality of processing devices. Such a processing device may be a microprocessor, micro-controller, digital signal processor, microcomputer, central processing unit, field programmable gate array, programmable logic device, state machine, logic circuitry, analog circuitry, digital circuitry, and/or any device that manipulates signals (analog and/or digital) based on operational instructions. Any such processing module can also be coupled to a memory. Such a memory may be a single memory device or a plurality of memory devices. Such a memory device may be a read-only memory, random access memory, volatile memory, non-volatile memory, static memory, dynamic memory, flash memory, and/or any device that stores digital information. Note that when such a processing module implements one or more of its functions via a state machine, analog circuitry, digital circuitry, and/or logic circuitry, the memory storing the, corresponding operational instructions is embedded with the circuitry comprising the state machine, analog circuitry, digital circuitry, and/or logic circuitry. The memory stores, and the processing module executes, operational instructions corresponding to at least some of the steps and/or functions illustrated herein. Alternatively, it is noted that such a processing module may include an embedded memory (or memories) that is operable to assist in the operations analogous to an external memory as described above.

Various embodiments of the invention include components of an error correction code (ECC) architecture that is operable to share two banks of registers. As discussed above, the prior art approaches necessitate 3 banks of registers. In certain embodiments, the number of registers in each bank is t (where t is the symbol correction capability of the RS code). For example, within the prior art, it is asserted that a 12-bit ECC with t=120 would consume approximately 500 k gates. This is supposedly for both the syndrome/symbol computer and the Reed-Solomon ECC decoder.

In accordance with various aspects of the invention, these 2 banks of registers can be employed to perform all ELP (error location polynomial) computations, EVP (error value (or magnitude) polynomial) computation, as well as the error location search operations (e.g., Chien search operations in one embodiment). This ECC Reed-Solomon ECC decoder architecture produces very efficient results with respect to silicon area consumption when compared to the prior art approaches. For example, one embodiment designed in accordance with the invention is operable to implement an entire 12-bit (t=120) Reed-Solomon ECC system for HDD applications which consumes only approximately 170 k gates. Of these 170 k gates, 70K gates are attributed to the syndrome/symbol computer. Again, others within the prior art assert that a comparable ECC system would consume approximately 500 k gates.

Various embodiments of the invention employ an architecture for a Reed-Solomon ECC decoder that is very efficient with respect to silicon area and power consumption. The area savings are especially evident with large scale ECC decoder designs.

FIG. 6 illustrates an embodiment of error location polynomial generation 600 being performed using only 2 banks of registers in accordance with decoding of a RS coded signal. In this embodiment, an error locator polynomial generation module 620 is operable to generate the error location polynomial employed in accordance with RS decoding. The error locator polynomial generation module 620 can be coupled to a memory 621 to assist in the operations required to perform its particular functions as described above with respect to other embodiments.

A decoder that performs the error location polynomial generation 600 can employ the Berlekamp-Massey decoding processing when decoding a RS coded signal. As can be seen, no more than a first plurality of registers 640 and a second plurality of registers 650 are required for use in storing error location polynomial coefficients that are employed during the generation of the error location polynomial. For example, the error locator polynomial generation module 620 is operable to generate the error location polynomial that is based on a discrepancy that is based on syndromes that correspond to a received codeword of a RS coded signal that is being decoded. As can also be seen, the first plurality of registers 640 includes a number of registers as depicted by register 641, register 642, . . . , and a register 643. Similarly, the second plurality of registers 650 includes a number of registers as depicted by register 651, register 652, . . . , and a register 653. In some desired embodiments, each of the first plurality of registers 640 and a second plurality of registers 650 includes a same number of registers; each has the same number of registers.

The coefficients of the error location polynomial can generally be referred to as σ. To update the error location polynomial coefficients in the generation of the error location polynomial, there are the previous error location polynomial coefficients (σ_(p)) [which can be stored in a first plurality of registers or “source” registers], the current error location polynomial coefficients (σ_(c)) [which can be stored in a second plurality of registers or “destination” registers], and the new error location polynomial coefficients (which then is the “current error location polynomial coefficients (σ_(c))” for the next iteration, and which gets stored in the first plurality of registers or “source” registers). In using the Berlekamp-Massey processing, one of two operations is performed on the first plurality of registers or “source” registers. The first plurality of registers or “source” registers takes on one of two possible values during each iteration: [1] it retains the values of the previous error location polynomial coefficients (σ_(p)) after having undergone shifting or [2] it takes on the values of the current error location polynomial coefficients (σ_(c)) after having undergone shifting.

In both cases, the purpose for shifting the first plurality of registers or “source” registers in this Berlekamp-Massey variant is to account for the X^(c-p) product in the classical σ_(c) computation (e.g., where c is the iteration counter that corresponds to the current iteration, and p corresponds to the previous iteration). When using this variant of Berlekamp-Massey processing, care must be now taken to ensure that σ_(p) is only shifted after iterations with non-zero discrepancies. And, when (one or more) intermediate zero discrepancies, is discovered followed by a non-zero discrepancy, multiple shifts in σ_(p) must be performed at that time to account for the intermediate zero discrepancies that occurred.

More details of this Berlekamp-Massey variant are provided below.

FIG. 7 illustrates an embodiment of a variant of Berlekamp-Massey decoding processing that can be employed when decoding a RS coded signal. As shown in a block 702, initialization is performed in which a number of values are set to predetermined values. The values in a number of registers are set to these predetermined values. For example, the 0^(th) value (i=0) of the current error location polynomial coefficients (σ_(c)(0)) and the 1^(st) value (i=1) of the previous error location polynomial coefficients (σ_(p)(1)) are set to 1 (e.g., σ_(c)(0)=σ_(p)(1)=1). It is also noted that since the values of σ_(c)(0) and σ_(p)(0) are always known (e.g., σ_(c)(0)=1 and σ_(p)(0)=0), memory locations need not be used to store these values. This can result iteration, but also information corresponding to a shift in X (e.g., X^(c-p)) that has been performed.

Afterwards, in a decision block 708, it is determined if the previous degree (degree(p)) is greater than the current degree (degree(c)). If yes in decision block 708, then a number of registers are set. For example, the next degree (degree(next)) is set to the value of the previous degree (degree(p)) in a block 710. The previous degree (degree(p)) is set to the value of the current degree (degree(c)) in a block 712. The current degree (degree(c)) is set to the value of the next degree (degree(next)) in a block 714. In an actual implementation, the operations of the blocks 710, 712, and 714 merely can involves swapping the values of the current degree (degree(c)) with the value of the previous degree (degree(p)).

The inverse value of Δp is set to the inverse value of the discrepancy (Δc) in a block 716. The previous values of the error location polynomial coefficients (σ_(p)(x)) are set to the current values of the error location polynomial coefficients (σ_(c)(x)) in a block 718. Then, the next values of the error location polynomial coefficients (σ_(next)(x)) are then set to the current values of the error location polynomial coefficients (σ_(c)(x)) in a block 720.

Referring back to the decision block 708: if no in decision block 708, then this variant of Berlekamp-Massey decoding processing continues directly to block 720, and then to the block 722 where the discrepancy (Δc) is computed.

This variant of Berlekamp-Massey decoding processing then continues to decision block 724 where it is determined if the current iteration is the 2T^(th) iteration (e.g., it is determined if this is within the correction power of the code by determining if c=2T). If no in decision block 724, then a number of other register values are updated. The previous error location polynomial coefficients (σ_(p)(x)) are set to a value of the previous error location polynomial coefficients (σ_(p)(x)) times “x” (e.g., σ_(p)(x)=x×σ_(p)(x)). The discrepancy ratio (Δc/Δp) is then computed in a block 730. The inverse of the discrepancy (Δc) (e.g., 1/Δc) is begun to be computed in a block 732 (e.g., (1/Δc)*). Then, the iteration is incremented (e.g., c=c+1) in a block 734. in memory/register use savings because of these known constant values, in that, these constant values need not be stored to perform the decoding processing.

For all other values if i, the values of the current error location polynomial coefficients (σ_(c)(i)) and the values of the previous error location polynomial coefficients (σ_(p)(i)), are all set to 0 (e.g., σ_(c)(i)=σ_(p)(i)=0). Because the initial values of the 0^(th) iteration are known beforehand, then the current degree (degree(c)) is initially set to 1, and the discrepancy (Δc) as well as the discrepancy ratio (Δc/Δp) are both set to the value of the 0^(th) syndrome (e.g., the least significant syndrome) that corresponds to the codeword of a received signal.

Then, in a decision block 704, it is determined if the discrepancy (Δc) is 0. If yes in decision block 704, then this variant of Berlekamp-Massey decoding processing continues to block 722 where the discrepancy (Δc) is computed. The discrepancy (Δc) is computed as follows:

Δc=S _(c)+Σ(σ_(c)(j)×S _(j)); for j≦N.

If no in decision block 704, then this variant of Berlekamp-Massey decoding processing continues to block 706 where sigma (σ) calculation is performed. The sigma (σ) value calculation can be performed as follows:

σ_(next)(x)=σ_(c)(x)+(Δc/Δp)×σ_(p)(x).

It is noted that, in some embodiments that employ 1 or more arithmetic logic units (ALUs), those ALUs can be employed to perform the calculations in the blocks 722 and 706.

The next values of the error location polynomial coefficients (σ_(next)(x)) are calculated using the current error location polynomial coefficients (σ_(c)(x)), the previous error location polynomial coefficients (σ_(p)(x)), and the discrepancy ratio (Δc/Δp) as follows:

σ_(next)(x)=Δ_(c)(x)+(Δc/Δp)×σ_(p)(x).

It is noted that the previous error location polynomial coefficients (σ_(p)(x)) is in fact a working variable that includes information corresponding not only to a previous Subsequently, the previous degree is updated if needed in a block 736 (e.g., previous degree (degree(p)=degree(p)+1), and this variant of Berlekamp-Massey decoding processing continues back to the decision block 704.

Referring back to the decision block 724: if yes in decision block 724, then this variant of Berlekamp-Massey decoding processing continues to a decision block 726 where it is determined if both the discrepancy (Δc) is equal to zero and if the current degree(c) is less than or equal to T. If yes in decision block 726, then this variant of Berlekamp-Massey decoding processing determines that any errors in the RS coded signal are correctable. If no in decision block 726, then this variant of Berlekamp-Massey decoding processing determines that any errors in the RS coded signal are not correctable (e.g., uncorrectable).

From certain perspectives, it can be noted that there are three separate states that operate in accordance with this variant of Berlekamp-Massey decoding processing: a loop state, a discrepancy state, and a sigma calculation state. From this perspective, the loop state includes at least the operations in the blocks 724, 728, 730, 732, 734, and 736; the discrepancy state includes the operation in the block 722; and the sigma calculation state includes at least states 706, 708, 710, 712, 714, 716, 718, and 720.

In certain embodiments, it is also noted that operations of the blocks 706, 720 and 718 can all be performed as a single operation with the use of at least one flag and a pair of register banks (e.g., source and destination register banks).

Continuing on with RS decoding, there are numerous means by which the error values can be calculated (e.g., error magnitude calculation). One means is using the Forney approach, and another involves the approach as described in the following reference [1].

[1] R. Koetter, “On the determination of error values for codes from a class of maximal curves,” Proceedings Allerton Conference on Communication, Control, and Computing, University of Illinois at Urbana-Champaign, 1997.

During each iteration of a plurality of iterations employed to generate the error location polynomial, the error locator polynomial generation module 620 is operable to perform the following functions: retrieve a previous plurality of error location polynomial coefficients from the first plurality of registers 640, retrieve a current plurality of error location polynomial coefficients from the second plurality of registers 650, employ the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients, and store the new plurality of error location polynomial coefficients in the second plurality of registers 650. Such a decoder is operable to employ the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal.

FIG. 8 illustrates an embodiment of error location polynomial generation and error location searching 800 being performed using only 2 banks of registers in accordance with decoding of a RS coded signal. The error location searching re-uses some of those same banks of registers employed within error location polynomial generation in accordance with decoding of a RS coded signal; for example, the error location searching re-uses the register bank that stores the final plurality of error location polynomial coefficients. While the error location searching is being performed, the other register bank (e.g., the bank not being re-used specifically for error location searching) is employed to evaluate another set of coefficients to determine the corresponding error value each time an error location is found.

In this embodiment, an error locator polynomial generation module 820 is operable to generate the error location polynomial, and an error location search module 830 is operable to solve for the roots of the error locator polynomial in accordance with RS decoding. The error locator polynomial generation module 820 can be coupled to a memory 821 to assist in the operations required to perform its particular functions as described above with respect to other embodiments. Similarly, the error location search module 830 can be coupled to a memory 831 to assist in the operations required to perform its particular functions as described above with respect to other embodiments. The operations of the error location search module 830 can employ the Chien search approach 832, if desired in a particular embodiment.

A decoder that performs the error location polynomial generation and error location searching 800 can employ Berlekamp-Massey processing, Euclid processing, or another means when generating the error location polynomial and can also employ a variety of means for error location searching (including Chien searching) in accordance with decoding of a RS coded signal. As can be seen, no more than a first plurality of registers 840 and a second plurality of registers 850 are required for use in storing error location polynomial coefficients that are employed during the generation of the error location polynomial, and then these same first plurality of registers 840 and second plurality of registers 850 are employed again for performing the error location search operations, which can be performed using the Chien search approach 832, if desired.

For example, the error locator polynomial generation module 820 is operable to generate the error location polynomial that is based on a discrepancy that is based on syndromes that correspond to a received codeword of a RS coded signal that is being decoded. As can also be seen, the first plurality of registers 840 includes a number of registers as depicted by register 841, register 842, . . . , and a register 843. Similarly, the second plurality of registers 850 includes a number of registers as depicted by register 851, register 852, . . . , and a register 853. In some desired embodiments, each of the first plurality of registers 840 and a second plurality of registers 850 includes a same number of registers; each has the same number of registers.

Then, during the error location search operations, the error location search module 830 is operable to process the error location polynomial to locate an error within the RS coded signal. The error location search module 830 is operable to employ at least one of the first plurality of registers 840 and the second plurality of registers 850 to store a plurality of evaluated coefficients corresponding to an error location when processing the error location polynomial. If desired, the error location search module 830 is operable to perform Chien searching (e.g., reference numeral 832) to process the error location polynomial to locate the error within the RS coded signal.

FIG. 9 illustrates an embodiment of a decoding architecture that employs Berlekamp-Massey decoding processing 900 when decoding a RS coded signal. With an architecture designed in accordance with this embodiment, the source (SRC) and destination (DEST) register banks are reused during error value polynomial (EVP) computation and error location search operation (e.g., during the Chien search operation). As can also be seen, a first plurality of registers 940 includes a number of registers as depicted by SRC(1), SRC(2), . . . , and a SRC(n). Polynomial multiplications by X^(c-p) are accomplished by shifting the source (SRC) register bank as required. Similarly, a second plurality of registers 950 includes a number of registers as depicted by DEST(1), DEST(2), . . . , and DEST(n). The first plurality of registers 940 is operable to store the previous plurality of error location polynomial coefficients (σ_(p)(x)), and the second plurality of registers 950 is operable to store the current plurality of error location polynomial coefficients (σ_(c)(x)). It is also noted that the error location polynomial is based the computed discrepancy which is based, in part, on the syndromes that correspond to a received codeword of the RS coded signal. These syndromes can be stored in a plurality of syndrome registers 910 as depicted by SYN(0), SYN(1), . . . , SYN(2 n-2), and SYN(2 n-1). As can be seen in the diagram, selections of syndromes for discrepancy computations from the plurality of syndrome registers 910 is performed by modifying the plurality of syndrome registers 910 by wrap-around shifting; this obviates the need to perform multiplexing (e.g., resulting in the saving of gates) or some other form of modification of the plurality of syndrome registers 910 to perform the appropriate selection of syndromes.

A plurality of arithmetic logic units (ALUs) 960 as depicted by ALU(1), ALU(2), . . . , ALU(n) is operable to perform certain of the calculations required in performing both the error location polynomial generation and error value computation. One of the operations the plurality of ALUs 960 performs is the calculation of the values of sigma (σ) (which is based on the values in the first plurality of registers 940, the second plurality of registers 950, and the discrepancy ratio); another one of the operations the plurality of ALUs 960 performs is calculation of the discrepancy (which is based on the current sigma iteration and a selected set of syndromes). The discrepancy is generated using a summation of selected syndromes multiplied by corresponding sigma (σ) coefficients.

While a plurality of ALUs 960 is depicted here, it is noted that as few as a single ALU could be employed sequentially to perform the calculations for each of the corresponding registers. Alternatively, as many as one ALU could be employed for each to perform the calculations for each of the corresponding registers in a fully parallel implementation. Moreover, other number of ALUs can also be employed thereby giving a designer the ability to consider various cost performance trade-offs (e.g., various degrees of parallelism).

When performing the division operations in accordance with generating the error location polynomial, a divider 930 employs an inverter and a multiplier. This implementation of division is much cheaper than a single-cycle implemented divider in hardware. One of the reasons that such a divider 930 (inverter and multiplier) can be employed herein because of the pipelined arrangement of the decoding processing. For example, the division processing can be afforded slightly more time herein when compared to prior art approaches. This allows for the use of multiple clock cycles to perform the inversion processing, and inversion is much cheaper to implement than a single-cycle implemented divider in hardware. A state machine 920 is also employed to coordinate and govern the operations within the decoding processing.

As can be seen, the total number of registers required is slightly more than 4n, where n is the hardware correction power and n≦t; it is noted that t is the ECC software correction power. It is noted that this diagram corresponds to the ECC decoder and does not include the symbol/syndrome computer module. When also including the symbol/syndrome computer module, then total number of registers required would be slightly more than 6n.

In accordance with certain embodiments of decoding of a RS coded signal, it may be required to compute the error value polynomial, which is also referred to as the error magnitude polynomial. If this is a requirement, the value in the DEST register bank (reference numeral 950) may be moved into the SRC register bank (reference numeral 940) so that the error value polynomial can be computed and stored in the DEST register bank. However, some implementations may not require generation of the error value polynomial at all.

The next step is to evaluate the error location polynomial in order to determine the locations of all errors (i.e., perform the error location search operations). This can be performed using a Chien search operation in some embodiments. As mentioned above, the error location search operations (e.g., the Chien search) can be performed using the existing SRC (first plurality of registers 940) and DEST (second plurality of registers 950) register banks. In one embodiment of a HDD application, it is noted that this re-using of the same register banks can be performed provided that an entire ECC correction can be completed within the worst-case sector transfer time.

FIG. 10 illustrates an embodiment of a error location searching and error magnitude (value) calculation 1000 in accordance with decoding of a RS coded signal. This embodiment depicts one embodiment of a configuration of the hardware required for performing the error location search operations (e.g., the Chien search) as well as the error magnitude calculation operations (i.e., computing the error values). Analogous to the previous embodiment, it is noted that the division operations in accordance with performing the error value calculation can also employ a divider 1030 employs an inverter and a multiplier. It is noted that the divider 1030 can be the same divider 930 of the previous embodiment; in other words, the divider 930 can be re-used for error value computation, if desired.

Again, such an implementation of division is much cheaper than a single-cycle implemented divider in hardware, and the pipelined arrangement of the decoding processing allows for the use of such a divider 1030 (inverter and multiplier). In this embodiment, Chien searching is performed, and a Chien search state machine 1020 is employed to coordinate and govern the operations of the error location search operation within the decoding processing.

The error location search operations employ a first plurality of registers 1040 and a second plurality of registers 1050 that are employed within the error location polynomial generation operations. The first plurality of registers 1040 is operable to store a first plurality of evaluated coefficients (e.g., a previous group) corresponding to each error location when processing the error location polynomial (σ_(p)(x)), shown as σ_(p)(1), σ_(p)(2), . . . , σ_(p)(n-1), and σ_(p)(n). The second plurality of registers 1050 is operable to store a second plurality of evaluated coefficients corresponding to each error location when processing the error location polynomial (e.g., a current group) (σ_(c)(x)), shown as σ_(c)(1), σ_(c)(2), . . . , σ_(c)(n-1), and σ_(c)(n).

The additional hardware required to perform a Chien search and compute error values (reference numeral 1031) includes constant (α) multipliers (shown as ×α), XOR trees and control logic. The divider and registers can be shared with the error location polynomial generation operations (e.g., the compute ELP function).

It is noted that various degrees of parallelism can be employed when doing error location searching (e.g., when doing Chien searching) in order to reduce evaluation time. Alternative to the embodiment shown in this diagram, multiple alpha (a) multipliers can be employed between the output of the registers and the input of the registers (e.g., multiple “×α” blocks could be employed instead of a singular “×α” block for each register). If this multiple alpha (α) multipliers are employed, then access to each intermediate result (i.e., each result after each alpha (α) multiplier) must be accessible for Chien searching evaluation. For example, multiple XOR trees would then operate on each intermediate result point to allow that point's evaluation in Chien searching.

It is also noted with respect to this diagram that while (σ_(p)(x)) is shown within the first plurality of registers 1040, the actual values in these registers are the coefficients of some polynomial that is employed to compute error values at each error location.

FIG. 11 illustrates an embodiment of a method 1100 that is operable to employ Berlekamp-Massey decoding processing when decoding a RS coded signal. The method involves generating an error location polynomial that is based on a discrepancy that is based on a plurality of syndromes that corresponds to a received codeword of the RS coded signal as shown in a block 1110. Then, for each iteration of a plurality of iterations employed to generate the error location polynomial, the method 1100 performs a number of operations.

The method 1100 involves retrieving a previous plurality of error location polynomial coefficients from a first plurality of registers (as shown in a block 1120) and also retrieving a current plurality of error location polynomial coefficients from a second plurality of registers (as shown in a block 1130).

The method 1100 then operate by employing the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients, as shown in a block 1140.

Once these new plurality of error location polynomial coefficients have been calculated, the method 1100 operate by storing the new plurality of error location polynomial coefficients in the second plurality of registers, as shown in a block 1150. It is noted that no more than the first plurality of registers and the second plurality of registers are employed for use in storing error location polynomial coefficients. The method 1100 then continues by employing the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal, as shown in a block 1160.

In an embodiment alternative to the 1100, a method could be implemented thereby performing Chien searching to process the error location polynomial to locate an error within the RS coded signal, and thereafter employing at least one of the first plurality of registers and the second plurality of registers to store a plurality of evaluated coefficients corresponding to each error location when processing the error location polynomial.

Any division operations performed in accordance with the method 1100 can also be performed using an inverter and a multiplier to effectuate the dividing operation. For example, the method 1100 can operate by inverting at least one coefficient of the previous plurality of error location polynomial coefficients, and then multiplying the inverted at least one coefficient of the previous plurality of error location polynomial coefficients and at least one coefficient of the current plurality of error location polynomial coefficients thereby calculating the discrepancy ratio.

It is also noted that, although parameterization helps achieve minimal area goals for such a decoder architecture as described herein, while still meeting the architectural constraints, some embodiment of the this design can include components which cannot be parameterized. It is noted also that various embodiments and variations of the Berlekamp-Massey processing in accordance with decoding of a RS coded signal can also be employed without departing from the scope and spirit of the invention.

The present invention has also been described above with the aid of method steps illustrating the performance of specified functions and relationships thereof. The boundaries and sequence of these functional building blocks and method steps have been arbitrarily defined herein for convenience of description. Alternate boundaries and sequences can be defined so long as the specified functions and relationships are appropriately performed. Any such alternate boundaries or sequences are thus within the scope and spirit of the claimed invention.

The present invention has been described above with the aid of functional building blocks illustrating the performance of certain significant functions. The boundaries of these functional building blocks have been arbitrarily defined for convenience of description. Alternate boundaries could be defined as long as the certain significant functions are appropriately performed. Similarly, flow diagram blocks may also have been arbitrarily defined herein to illustrate certain significant functionality. To the extent used, the flow diagram block boundaries and sequence could have been defined otherwise and still perform the certain significant functionality. Such alternate definitions of both functional building blocks and flow diagram blocks and sequences are thus within the scope and spirit of the claimed invention.

One of average skill in the art will also recognize that the functional building blocks, and other illustrative blocks, modules and components herein, can be implemented as illustrated or by discrete components, application specific integrated circuits, processors executing appropriate software and the like or any combination thereof.

Moreover, although described in detail for purposes of clarity and understanding by way of the aforementioned embodiments, the present invention is not limited to such embodiments. It will be obvious to one of average skill in the art that various changes and modifications may be practiced within the spirit and scope of the invention, as limited only by the scope of the appended claims. 

1. A decoder that is operable to employ Berlekamp-Massey decoding processing when decoding a Reed-Solomon (RS) coded signal, comprising: no more than a first plurality of registers and a second plurality of registers for use in storing error location polynomial coefficients; and an error locator polynomial generation module that is operable to generate an error location polynomial based on a plurality of syndromes that corresponds to a received codeword of the RS coded signal; and wherein: during each iteration of a plurality of iterations, the error locator polynomial generation module is operable to: retrieve a previous plurality of error location polynomial coefficients from the first plurality of registers; retrieve a current plurality of error location polynomial coefficients from the second plurality of registers; employ the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients; and store the new plurality of error location polynomial coefficients in the second plurality of registers; and the decoder is operable to employ the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal.
 2. The decoder of claim 1, further comprising: an error location search module that is operable to process the error location polynomial to locate an error within the RS coded signal; and wherein: the error location search module is operable to employ at least one of the first plurality of registers and the second plurality of registers to store a plurality of evaluated coefficients corresponding to the error location when processing the error location polynomial.
 3. The decoder of claim 1, further comprising: an error location search module that is operable to process the error location polynomial to locate an error within the RS coded signal; and wherein: the error location search module is operable to perform Chien searching to process the error location polynomial to locate the error within the RS coded signal.
 4. The decoder of claim 1, further comprising: an inverter and a multiplier that cooperatively perform calculation of a discrepancy ratio for use when calculating the new plurality of error location polynomial coefficients; and wherein: the inverter is operable to invert a current discrepancy that is based on the current plurality of error location polynomial coefficients and a set of syndromes that correspond to the received codeword of the RS coded signal thereby generating an inverted previous discrepancy; and the multiplier is operable to multiply the an inverted previous discrepancy and a discrepancy of a current iteration thereby generating the discrepancy ratio.
 5. The decoder of claim 1, wherein: when a discrepancy corresponding to a current iteration and syndromes is non-zero, then the decoder is operable to perform calculation of a discrepancy ratio for use when calculating the new plurality of error location polynomial coefficients.
 6. The decoder of claim 1, wherein: increasing a degree of the error location polynomial by a value of 1 is performed by shifting the previous plurality of error location polynomial coefficients by
 1. 7. The decoder of claim 1, wherein: the first plurality of registers includes n registers, where n is an integer; and the second plurality of registers also includes n registers.
 8. The decoder of claim 1, wherein: the decoder is implemented within a communication device; and the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
 9. The decoder of claim 1, wherein: the RS coded signal is received from a communication channel.
 10. The decoder of claim 1, wherein: the RS coded signal is read from a storage media of a hard disk drive (HDD).
 11. A decoder that is operable to employ Berlekamp-Massey processing when decoding a Reed-Solomon (RS) coded signal, comprising: no more than a first plurality of registers and a second plurality of registers for use in storing error location polynomial coefficients, wherein each of the first plurality of registers and the second plurality of registers includes n registers and n is an integer; an error locator polynomial generation module that is operable to generate an error location polynomial based on a plurality of syndromes that corresponds to a received codeword of the RS coded signal; an error location search module that is operable to process the error location polynomial to locate an error within the RS coded signal; and wherein: the error location search module is operable to perform Chien searching to process the error location polynomial to locate the error within the RS coded signal; and wherein: during each iteration of a plurality of iterations, the error locator polynomial generation module is operable to: retrieve a previous plurality of error location polynomial coefficients from the first plurality of registers; retrieve a current plurality of error location polynomial coefficients from the second plurality of registers; employ the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients; and store the new plurality of error location polynomial coefficients in the second plurality of registers; and the decoder is operable to employ the error location polynomial and the location of the error when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal.
 12. The decoder of claim 11, wherein: the error location search module is operable to employ at least one of the first plurality of registers and the second plurality of registers to store a plurality of evaluated coefficients corresponding to the error location when processing the error location polynomial.
 13. The decoder of claim 11, further comprising: an inverter and a multiplier that cooperatively perform calculation of a discrepancy ratio for use when calculating the new plurality of error location polynomial coefficients; and wherein: the inverter is operable to invert a current discrepancy that is based on the current plurality of error location polynomial coefficients and a set of syndromes that correspond to the received codeword of the RS coded signal thereby generating an inverted previous discrepancy; and the multiplier is operable to multiply the an inverted previous discrepancy and a discrepancy of a current iteration thereby generating the discrepancy ratio.
 14. The decoder of claim 11, wherein: when a discrepancy corresponding to a current iteration and syndromes is non-zero, then the decoder is operable to perform calculation of a discrepancy ratio for use when calculating the new plurality of error location polynomial coefficients.
 15. The decoder of claim 11, wherein: increasing a degree of the error location polynomial by a value of 1 is performed by shifting the previous plurality of error location polynomial coefficients by
 1. 16. The decoder of claim 11, wherein: the decoder is implemented within a communication device; and the communication device is implemented within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
 17. The decoder of claim 11, wherein: the RS coded signal is read from a storage media of a hard disk drive (HDD).
 18. A method that is operable to employ Berlekamp-Massey decoding processing when decoding a Reed-Solomon (RS) coded signal, the method comprising: generating an error location polynomial based on a plurality of syndromes that corresponds to a received codeword of the RS coded signal; and wherein: during each iteration of a plurality of iterations: retrieving a previous plurality of error location polynomial coefficients from a first plurality of registers; retrieving a current plurality of error location polynomial coefficients from a second plurality of registers; employing the current plurality of error location polynomial coefficients and the previous plurality of error location polynomial coefficients when calculating a new plurality of error location polynomial coefficients; and storing the new plurality of error location polynomial coefficients in the second plurality of registers, wherein no more than the first plurality of registers and the second plurality of registers are employed for use in storing error location polynomial coefficients; and employing the error location polynomial when performing Berlekamp-Massey decoding processing to make a best estimate of an information codeword encoded within the RS coded signal.
 19. The method of claim 18, further comprising: performing Chien searching to process the error location polynomial to locate an error within the RS coded signal; and employing at least one of the first plurality of registers and the second plurality of registers to store a plurality of evaluated coefficients corresponding to the error location when processing the error location polynomial.
 20. The method of claim 18, further comprising: inverting at least one coefficient of the current plurality of error location polynomial coefficients and a set of syndromes that correspond to the received codeword of the RS coded signal thereby generating an inverted previous discrepancy; and multiplying the an inverted previous discrepancy and a discrepancy of a current iteration thereby generating the discrepancy ratio. 